This invention relates to a specialized logic region in a programmable logic device for use in applications in which the specialized region may optionally not be used. More particularly, this invention relates to such a specialized region having a low-power mode for applications in which it is not being used. Most particularly, this invention relates to an multiplier/accumulator region having such a low-power mode.
It is known in programmable logic devices to provide many logic regions, some of which may not be used in a particular user configuration. If a logic region is not used, but signals nevertheless are routed to that region, the capacitances of the various transistors and other components within that region will continually be charged and discharged, consuming power unnecessarily. However, typically, signals simply are not routed to the regions that are not being used.
More recently, there has been interest in providing, on a programmable logic device, regions particularly well suited to particular functions. The user, in programming the device, could elect to use those regions if those particular functions were required. Preferably, those regions would be flexible, so that even within the regions there would be elements that the user program could select to use or not use.
In such a case, signals would be routed to the region, and may reach elements within the region that are not used, consuming power unnecessarily as described above.
In view of the foregoing it would be desirable to be able to provide a programmable logic device having specialized regions within which components that are not used consume less power.